FIG. 1a illustrates a cross section of an integrated circuit (IC) employing multilevel metallization. A level of metallization contains electrical connections between elements in an IC. ICs can be manufactured having several layers of metallization to facilitate the increasing complexity and small size of microprocessors and other ICs.
An IC 100 has three layers of metallization 102, 104, and 106. The layers 102, 104, and 106 can be built on top of a single crystal silicon or other substrate 108. The substrate 108 can have semiconductor devices, such as transistors 110 and 112, formed in it. The layers 102, 104, and 106 can include conductive as well as insulating materials to isolate the conductive materials. The conductive materials, such as aluminum or copper, can form conductive lines connecting semiconductor devices such as the transistors 110 and 112, and can be separated and isolated by an insulating interlayer or interlevel dielectric (ILD) comprising a material such as silicon dioxide (SiO2). ILDs 114, 116, and 118 isolate conductive lines from each other and prevent cross-talk and electrical shorts. The IC 100 has several conductive lines, including interconnects 120, 122, 124, 126, 128, 130, and 132, vias 134 and 136, and contacts 138 and 140. The ILDs 114, 116, and 118 can have recessed features such as trenches and vias. Trenches can allow for the interconnects 120–132, which can connect different regions of the IC. Vias 134 and 136 can create electrical connections between the interconnects 120–132, and the contacts 138 and 140 can create connections with the transistors 110 and 112.
A damascene process can create either a trench or a via. A dual damascene process can create both a trench and a via at the same time by creating a via within a trench. Prior processes for fabricating conductive lines might have involved depositing a conductive material over an entire surface and etching away the excess material. This is a subtractive process. The damascene and dual damascene processes create trenches and/or vias in an ILD first, and then deposit metal in the trenches and vias. Excess metal is then removed. These processes are additive rather than subtractive.
FIGS. 1b, 1c, and 1d illustrate a dual damascene process. In FIG. 1b, trenches and vias have been created in an ILD. A layer 150 may have an ILD 152 having several trenches 154, 156, 158, and 160. The ILD 152 may also be patterned to hold vias such as via 162. In FIG. 1c, metal has been deposited on the ILD 152. When a material is being deposited in a trench or via, the deposition process usually leaves excess material 168 on a top surface 170 of the ILD 152. The excess material is typically removed using a chemical mechanical polishing (CMP) process. The CMP process uses a chemical slurry and a rotating polishing pad to polish the top surface 170 of the ILD 152. The rotating polishing pad removes the excess metal material 168 and planarizes the top surface 170 of the ILD 152.
An ILD 152 having a high dielectric constant (k) may be undesirable in many applications because a high-k ILD can promote capacitive coupling between conductive lines. Reducing the resistance and capacitance experienced by interconnects can increase the propagation speed of the signals that travel through the interconnects. Resistance is reduced by using copper rather than aluminum as an interconnect metal, and capacitance can be reduced by using a low-k ILD. SiO2 has a k of approximately 4.0. ILDs having a k of less than 4.0 are generally considered to be low-k.
Thus, in many ICs it may be desirable to use low-k ILDs in order to reduce capacitive coupling and propagation delay. One way to reduce the k of a material is to create pores or air pockets, because air has a very low k of approximately 1.0. However, low-k ILDs created in this way are mechanically weak. When CMP is performed on a low-k ILD, damage may occur to the ILD as a result of vibration and other mechanical forces and stresses caused by the rotating pad.
In FIG. 1d, material has been deposited in the trenches and vias and CMP has been performed to remove excess material. The deposition and subsequent CMP has created interconnects 172, 174, 176, and 178, and a via 180. The deposition of metal typically coats the up areas, or mesas, 170 with material, in addition to depositing material in the trenches 154, 156, 158, and 160. CMP can create various deformities in the ILD 152 such as a sheer induced via failure 182, a surface crack 184, subsurface delamination 186, and line-to-line “bent line” shorts. This damage can be caused by the stresses from mechanical polishing and the porosity of a low-K ILD 152. This physical damage can render an IC 100 useless, as it can cause electrical shorts and other problems.